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spamiam wrote:
Hmm, it is too bad that even with the USB->Serial breakout board that the speed was only reliably increased by a factor of 2. Do you think that the baud rate error is created on the FPGA side by an improper main clock speed? By that I mean that there is no good way to scale the 50MHZ main clock down to 460800 with adequate precision?Yes there is some inaccuracy in the clock because the divisor does not result in an integer. What happens is that the error accumulates until eventually it is out of spec and that ends the transmission. For higher baud rates the error factor is higher so it is reached with smaller data sizes. It is possible to send at 460,800 baud but only for very small capture depths (which defeats the object). It could be possible to insert code to reduce the error accumulation but that will take some more time to design and implement. I provided this speed improvement for testing purposes only.
I think I have a serial card on my computer that is capable of 230K 460K baud, and maybe 921K Can I just not use the USB converter and just plug in my serial cable and try it that way?Yes it can work that way in which case do not use the la.ucf changes for the TX/RX signals. Guiseppo is having trouble making that work so I would be interested in your result. I can also try it myself later today.
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